Join the leading chiplet interconnect startup! We are seeking an experienced Senior/Staff Packaging Engineer specializing in electro-thermal simulation to join our advanced packaging team. You will develop comprehensive thermal and electrical simulations for next-generation semiconductor packaging solutions, including 2.5D/3D IC integration, chiplet-based systems, and advanced heterogeneous integration technologies. This role is critical in enabling high-performance computing, AI accelerators, and advanced chiplet architectures. We offer a fun work environment with excellent benefits. ONSITE M-F
Key Responsibilities:
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Develop detailed thermal models for 2.5D/3D IC packages, chiplets, and multi-die systems; perform steady-state and transient thermal analysis with hotspot identification
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Execute power integrity (PI) and IR drop analysis; optimize power distribution networks (PDN) and power delivery architectures
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Conduct electromigration (EM) and reliability analysis for interconnects, bumps, TSVs, and redistribution layers (RDL)
Create hierarchical compact macro models (CMM) and reduced-order thermal models for earlystage design optimization
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Automate simulation workflows using Python, TCL, and Shell scripting; build design space exploration tools
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Collaborate with silicon design, package design, and manufacturing teams on design-for-reliability (DFR) initiatives
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Support customer engagements with technical analysis and present findings to stakeholders
Minimum Qualifications:
Education:
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PhD in Electrical/Mechanical Engineering, or related field with focus on thermal management, power delivery, or electronic packaging (Master’s with 5+ years experience considered)
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Strong academic background in power integrity, signal integrity, and thermal management for advanced packaging