DV - Staff (+) Verification Engineer - AMS modeling
Location
Bay Area, Vancouver or Toronto
Work mode
on-site
Type
full-time
Department
Engineering
Last seen
1d ago
Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You’ll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
•
Develop and execute RNM AMS model for best in class PHYs.
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Make sure the quality of models reflects schemetics.
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Write and debug SystemVerilog/UVM compliant test cases
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Collaborate with design team to ensure design quality
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Expertise to understand analog blocks.
Required Qualifications:
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5+yrs relevant experience
•
BS in EE or related field.
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Deep analog design expertise
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Knowledge of SystemVerilog, test environment and assertion coding
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Experience in verifying mixed signal IPs
Preferred Qualifications:
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Experience with Formal verification with Jasper Gold or vc-formal