DV - Staff (+) Verification Engineer - AMS modeling
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Before you apply
LocationBay Area, Vancouver or Toronto
Work modeon-site
Typefull-time
SeniorityLead
Experience5+ yrs
DepartmentEngineering
Company size51–200 people
PostedMay 20, 2026 · 5mo ago
Verified live1d ago
May no longer be actively hiring
Posted by the company on May 20, 202695% of this company's open roles have been listed for 90+ days
At a glanceSummarised by Seekless from the posting.
5+ yrs relevant experience
BS in EE or related field
Deep analog design expertise
Knowledge of SystemVerilog, test environment and assertion coding
Experience in verifying mixed signal IPs
Experience with Formal verification with Jasper Gold or vc-formal
Python/Perl/Tcl scripting for design verification
Skills
SystemVerilog
UVM
Python
Perl
Tcl
Jasper Gold
vc-formal
About the role
Join the leading chiplet startup! As an Eliyan Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art AMS systemVerilog models (RNM) for best-in-class PHYs. You will own verification of AMS SystemVerilog models. This is a hands-on technical role. You’ll work with analog team, look at schematics and write the RNM models. We offer a fun work environment with excellent benefits. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
•
Develop and execute RNM AMS model for best in class PHYs.
•
Make sure the quality of models reflects schemetics.
•
Write and debug SystemVerilog/UVM compliant test cases
•
Collaborate with design team to ensure design quality
•
Expertise to understand analog blocks.
Required Qualifications:
•
5+yrs relevant experience
•
BS in EE or related field.
•
Deep analog design expertise
•
Knowledge of SystemVerilog, test environment and assertion coding
•
Experience in verifying mixed signal IPs
Preferred Qualifications:
•
Experience with Formal verification with Jasper Gold or vc-formal
•
Python/Perl/Tcl scripting for design verification
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