PD STA engineer
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Before you apply
LocationHaifa, Haifa District, Israel; Herzliya, Tel Aviv District, Israel
SeniorityMid
Experience4+ yrs
DepartmentHardware
Company size10,000+ people
PostedNov 2, 2026 · 2d ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
4+ years experience in Static Timing analysis
Extensive experience with one of the commercial STA tools
Familiarity with hierarchical design approach, top-down design, timing and physical convergence
Experience with backend STA closure and Signoff
Deep understanding of designs' constraints development
Good understanding of AC timing from specs to implementation
Good understanding of DFT modes and their constraints
Good communication skills and team player
Quick learning of flows and methods
Understanding noise and signal integrity effects
Timing margins fundamental from synthesis to signoff
Experience with scripting
About the role
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.
Description
You will be responsible for:
Develop/support automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows
Power optimizations
Generate block level budget and context for correlation with Full Chip
Drive custom IP integration and custom timing checks flows
Close work with Design, DFT, architecture and Power team
Minimum qualifications
•
4+ years experience in Static Timing analysis
•
Extensive experience with one of the commercial STA tools
•
Familiarity with hierarchical design approach, top-down design, timing and physical convergence
•
Experience with backend STA closure and Signoff
•
Deep understanding of designs’ constraints development
•
Good understanding of AC timing from specs to implementation
•
Good understanding of DFT modes and their constraints
•
Good communication skills and team player
•
Quick learning of flows and methods
Preferred qualifications
•
Advantage - Understanding noise and signal integrity effects
•
Advantage - Timing margins fundamental from synthesis to signoff
•
Advantage - Experience with scripting
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