Gate-level Noise (Signal Integrity) / STA CAD Engineer
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Before you apply
LocationAustin, Texas, United States; Sunnyvale, California, United States
Typefull-time
SeniorityMid
Experience3+ yrs
DepartmentHardware
Company size10,000+ people
PostedNov 2, 2026 · 1d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
BS in Electrical Engineering, Computer Engineering, or related technical discipline and 3+ years of industry experience
Background in gate-level signal integrity, with an emphasis on crosstalk glitch noise and static timing analysis (STA)
Hands-on experience with industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent)
Exposure to noise and timing sign-off on advanced process nodes
Experience with or exposure to noise and timing ECO flows and techniques for design closure
Scripting and automation skills in Python, Tcl, and/or Perl
Ability to coordinate and drive initiatives with appropriate guidance
Familiarity with standard cell library noise characterization (e.g., CCSN) or correlating gate-level models with SPICE simulations
Understanding of place-and-route (P&R) implementation engines and physical design convergence
Interest in modern AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage
Strong communication and presentation skills
Skills
PrimeTime-SI
Tempus
Python
Tcl
Perl
About the company
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There’s no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
About the role
As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.
Description
In this highly visible role, your primary responsibilities will include:
Contributing to the development of sign-off methodologies, noise margins, and tool qualification strategies for gate-level glitch noise and static timing analysis (STA) across advanced nodes.
Develop and maintain production CAD flows and scripts for core noise and STA tools, from constraint setup through tapeout sign-off.
Support the glitch noise analysis approach - including glitch thresholds, propagation, and its impact on timing and functional integrity.
Support root-cause analysis of crosstalk glitch and timing anomalies, using and helping build automated triage workflows and AI-agent pipelines to improve debug efficiency.
Collaborate with and support design and physical design teams on noise/timing constraints, flow issues, and sign-off waivers.
Support noise and timing ECO methodologies to help accelerate design convergence toward tapeout.
Participate in systematic tool and version qualifications, tracking QoR, performance, and correlation against golden baselines.
Help author documentation and guidelines and share noise and STA best practices with the team.
Minimum qualifications
•
BS in Electrical Engineering, Computer Engineering, or related technical discipline and 3+ years of industry experience.
Preferred qualifications
•
Background in gate-level signal integrity, with an emphasis on crosstalk glitch noise and static timing analysis (STA).
•
Hands-on experience with industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent).
•
Exposure to noise and timing sign-off on advanced process nodes.
•
Experience with or exposure to noise and timing ECO flows and techniques for design closure.
•
Scripting and automation skills in Python, Tcl, and/or Perl.
•
Ability to coordinate and drive initiatives with appropriate guidance.
•
Familiarity with standard cell library noise characterization (e.g., CCSN) or correlating gate-level models with SPICE simulations.
•
Understanding of place-and-route (P&R) implementation engines and physical design convergence.
•
Interest in modern AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.
•
Strong communication and presentation skills.
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