· Bachelor’s degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a closely related field is required; Master’s degree or PhD preferred.
· Minimum of 5 years of progressive experience in semiconductor packaging engineering, with a demonstrated track record of increasing technical responsibility.
· Demonstrated hands-on experience with advanced package formats relevant to discrete protection devices, including WLCSP, DFN, QFN, SOD, SOT, and flip-chip assemblies.
· Direct experience working with OSAT partners in a technical capacity, including process development, design rule definition, and supplier qualification activities.
· Proven experience executing JEDEC and AEC-Q101 reliability qualification programs, including test plan development, data analysis, and formal qualification reporting.
· Deep understanding of semiconductor assembly processes including wafer dicing, die attach, wire bonding, molding, plating, and wafer-level packaging processes such as WBC (wafer backside coating) and CDAF.
· Proficiency in failure analysis techniques including cross-sectioning, SEM/EDX, SAT (scanning acoustic tomography), and optical microscopy.
· Working knowledge of package-level electrical and thermal simulation tools.
· Familiarity with statistical process control (SPC), CPK analysis, and DOE methodologies as applied to packaging process development.
· Understanding of ESD, TVS, and protection IC device physics and how package parasitics influence transient protection performance.
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Soft Skills & Other Requirements
· Strong technical communication skills with the ability to present complex packaging topics to both engineering peers and executive management.
· Ability to work effectively in a cross-functional, globally distributed team environment spanning design, manufacturing, quality, and commercial organizations.
· Willingness to travel domestically and internationally to OSAT and fabrication partner sites as needed